A validation method for the synchronization subsystem of a fault-tolerant computer system is presented. The high reliability requirement of flight-crucial systems precludes the use of most traditional validation methods. The method presented utilizes formal design proof to uncover design and coding errors and experimentation to validate the assumptions of the design proof. The experimental method is described and illustrated by validating the clock synchronization system of the Software Implemented Fault Tolerance computer. The design proof of the algorithm includes a theorem that defines the maximum skew between any two nonfaulty clocks in the system in terms of specific system parameters. Most of these parameters are deterministic. One crucial parameter is the upper bound on the clock read error, which is stochastic. The probability that this upper bound is exceeded is calculated from data obtained by the measurement of system parameters. This probability is then included in a detailed reliability analysis of the system.
Fault-Tolerant Clock Synchronization Validation Methodology
1987-11-01
Miscellaneous
No indication
English
Fault-Tolerant Clock Synchronization for Safety-Critical Applications
British Library Conference Proceedings | 2004
|Fault-tolerant clock synchronization for safety-critical applications
Automotive engineering | 2004
|