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A ROUTING ALGORITHM AND A ROUTER ARCHITECTURE FOR 3D NOC
Development of memory controller for today’s Elbrus microprocessors
Design A Congestion Aware Routing Algorithm for Synchronous Cam Design
Pipelined Control-Path Effects on Area and Performance of a Wormhole-Switched Network-on-Chip
The approach to design of dynamically reconfigurable arbitration units in embedded systems
Design and implementation of secured agent based NoC using shortest path routing algorithm
A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs
HYBRID STRATEGY FOR SWITCHING REGULATE TRANSMISSION IN IMAGINARY CIRCUITS
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications
Router Architecture for Junction Based Source Routing:Design and FPGA Prototyping
EVALUATION OF SOURCE ROUTING FOR MESH TOPOLOGY NETWORK ON CHIP PLATFORMS