SEU In An Advanced Bipolar Integrated Circuit
Radiation Damage In Advanced Bipolar Transistors
Forward Bias Inhibits Single-Event Upsets
Refined Transistor Model For Simulation Of SEU
Calculating Second-Order Effects in MOSFET's
Analyzing Single-Event Gate Ruptures In Power MOSFET's
Spread Of Charge From Ion Tracks In Integrated Circuits
Internal Correction Of Errors In A DRAM
Estimating Rates Of Single-Event Upsets
Empirical Modeling Of Single-Event Upset
Predicting Lifetimes Of CMOS ASIC's From Test Data