This paper describes a low power low noise mixed analog-digital PDFE (particle detector front-end) custom chip developed by IMEC for ESA and intended for scientific energetic particle space born instrumentation (spectroscopy). The ASIC is designed in a standard 700 nm CMOS process. The chip comprises a charge sensitive amplifier, a semi-gaussian pulse-shaping amplifier, a peak detector, a discriminator, an 8-bit ADC and control logic. A second channel is provided for (anti-)coincidence purposes. For cost reasons, the circuit is made as versatile as possible by providing several digitally programmable configurations. ENC (equivalent noise charge) is 800 electrons rms at 100 pF detector capacitance, 1 nA leakage and a shaper peaking time of 1000 ns. Conversion gain is 30 mV/pF and full scale input is 0.1 pC. Power consumption is 50 mW when all blocks are enabled; power supply is 5 V. The die area measures 31 mm2. A baseline shift of 15 mV is realised at 250 Ksamples/s (this is the maximum counting rate) for inputs limited to 2.5 fC and at 25 Ksamples/s for full scale input. Radiation hardness is implemented both at the transistor level and at the architectural level.
PDFE: A particle detector front-end ASIC
2000
6 Seiten, 7 Bilder, 1 Tabelle, 6 Quellen
Aufsatz (Konferenz)
Englisch
Analog-Digital-Umsetzer , Betriebsspannung , Diskriminator , geringe Verlustleistung , Hybridschaltung , Koinzidenzschaltung , komplementäre MOS-Schaltung , kosmische Strahlung , Kundenschaltung , Leckstrom , Massenspektrometer , programmierbare logische Anordnung , Raumfahrt , Rauschunempfindlichkeit , Schaltungsentwurf , Strahlungsfestigkeit , Submikrometerbereich , Systemarchitektur , Teilchenzähler , Transistorverstärker
PDFE: A Particle Detector Front-End ASIC
British Library Conference Proceedings | 2000
|ASIC Physical Layout for the HCD ASIC
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