In two recent NASA-sponsored studies, the authors simulated a Bendix Avionics processor and conducted a series of fault injection experiments to determine the degree of fault latency in a redundant flight control system that employed comparison monitoring as the exclusive means of failure detection. The fault coverage of a typical self-test program was also determined. This paper summarizes the results of these studies. These studies demonstrated that: A self-test program should be designed to capitalize on the hardware mechanization of the processor; otherwise subtests tend to exercise the same hardware components, repeatedly, while neglecting to exercise a substantial proportion of the remainder. Fault latency is relatively independent of both length and instruction mix of a program. For example, a flight control program of 2200 assembly language instruction detected 79 % of all gate-level faults in 8 repetitions whereas a simple 44-instruction program detected 70 % in 8 repetitions. There is a significant difference in fault coverage assesssed using pin-level and gate-level fault models.


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    Titel :

    New results in fault latency modelling


    Weitere Titelangaben:

    Neue Ergebnisse in der Modellvorstellung der Fehlerlatenz


    Beteiligte:
    McGough, J.G. (Autor:in) / Swern, F.L. (Autor:in) / Bavuso, S. (Autor:in)


    Erscheinungsdatum :

    1983


    Format / Umfang :

    8 Seiten, 12 Bilder, 2 Tabellen, 3 Quellen


    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Print


    Sprache :

    Englisch




    New results in fault latency modelling

    MCGOUGH, J. / SWERN, F. / BAVUSO, S. | AIAA | 1983


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    Methodology for measurement of fault latency in a digital avionic miniprocessor

    McGough, J.G. / Swern, F. / Bavuso, J. | Tema Archiv | 1981