Convolutional neural networks (CNN) is a widely known deep learning architecture and achieves higher accuracies in speech processing and computer vision applications. CNN has arisen as best option in the fields such as video surveillance, mobile robot vision, smart factories, and medical diagnostics. CNN has shown its tremendous potential for image understanding in Cardio-Vascular (CV) systems. But, the tremendous potential of CNNs came up with additional computational burden. To get an outstanding performance of CNN-based algorithms, it requires large amount of enormous applications and memory resources. Matrix multiplication (MM) is the most fundamental computational operation taking place in CNN. Researchers in this field found that multiplication operation is the most resource-intensive and power-hungry operation in CNN. This work aims to design an FPGA-based CNN using systolic array which can improve both the accuracy and hardware efficiency of convolutional neural network. Here, we made design optimisation in multiplier unit which brings a significant impact on overall performance of convolutional neural networks.


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    Titel :

    Optimisation of FPGA-Based Designs for Convolutional Neural Networks


    Weitere Titelangaben:

    Lect. Notes Electrical Eng.


    Beteiligte:
    Chokkadi, Shreesha (Herausgeber:in) / Bandyopadhyay, Rajib (Herausgeber:in) / Bonifus, P. L. (Autor:in) / Thomas, Ann Mary (Autor:in) / Antony, Jobin K. (Autor:in)


    Erscheinungsdatum :

    2023-03-12


    Format / Umfang :

    13 pages





    Medientyp :

    Aufsatz/Kapitel (Buch)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




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