Local memory architecture plays an important role in high performance massively parallel vision chip. In this paper, we propose an enhanced memory architecture with compact circuit area designed in a full-custom flow. The memory consists of separate master-stage static latches and shared slave-stage dynamic latches. We use split transmission transistors on the input data path to enhance tolerance for charge sharing and to achieve random read/write capabilities. The memory is designed in a 0.18 μm CMOS process. The area overhead of the memory achieves 16.6 μm2/bit. Simulation results show that the maximum operating frequency reaches 410 MHz and the corresponding peak dynamic power consumption for a 64-bit memory unit is 190 μW under 1.8 V supply voltage.


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    Titel :

    Enhanced memory architecture for massively parallel vision chip


    Beteiligte:
    Chen, Zhe (Autor:in) / Yang, Jie (Autor:in) / Liu, Liyuan (Autor:in) / Wu, Nanjian (Autor:in)

    Kongress:

    Selected Papers from Conferences of the Photoelectronic Technology Committee of the Chinese Society of Astronautics 2014, Part II ; 2014 ; China,China


    Erschienen in:

    Erscheinungsdatum :

    13.04.2015





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




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