Low-level image processing operations usually involve simple and repetitive operations over the entire input images, thus image processor may communicate with the memory system or each other frequently, hence the image processor would provide high throughput rate. In this article we present an architectural design and analysis of a parallel RISC image processor. The processor was based on PCI bus to speed up a range of image processing operations. The other characteristic of the processor is that a new three-port hostbridge is integrated into the processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed.


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    Titel :

    Design of a parallel RISC image processor based on PCI bus


    Beteiligte:
    Jiang, Xianyang (Autor:in) / Shen, Xubang (Autor:in) / Zhang, Tianxu (Autor:in)

    Kongress:

    Neural Network and Distributed Processing ; 2001 ; Wuhan,China


    Erschienen in:

    Erscheinungsdatum :

    2001-09-20





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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