Currently, in image processing, segmentation algorithms comprise between real time video rate processing and accurate results. In this paper, we present an efficient and not recursive algorithm filter originated from Deriche filter. This algorithm is implemented in hardware by using FPGA technology. Thus, it permits video rate edge detection. In addition, the FPGA board is used as an edge tracking accelerator, it allows us to greatly reduce execution time by avoiding scanning the whole image. We also present the architecture of our vision system dedicated to build 3D scene every 200 ms.


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    Titel :

    Real-time reprogrammable low-level image processing: edge detection and edge tracking accelerator


    Beteiligte:
    Meribout, M. (Autor:in) / Hou, Kun M. (Autor:in)

    Kongress:

    Visual Communications and Image Processing '93 ; 1993 ; Cambridge,MA,United States


    Erschienen in:

    Erscheinungsdatum :

    1993-10-22





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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