As a cost effective solution to making microcontroller based systems “J1850[1] aware”, a peripheral device (the HIP7010) was developed to extend the capabilities of standard microcontrollers. From the perspective of the Host, the peripheral device handles J1850 messages as a series of bytes (similar in concept to a universal asynchronous receiver/transmitter [UART]).The architecture of the HIP7010 is discussed. The design of the J1850 interface, state machine, status/control blocks, cyclical redundancy check (CRC) hardware, host interface, and fail-safe features are detailed. Illustrations are provided of: Host/HIP7010 interfacing; message transmission and reception; error handling; and In-Frame Response (IFR) generation.


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    Titel :

    Architecture and Operation of the HIP7010 J1850 Byte-Level Interface Circuit


    Weitere Titelangaben:

    Sae Technical Papers


    Beteiligte:
    Stark, John (Autor:in) / Sferrazza, Paul (Autor:in) / Halter, Rick (Autor:in)

    Kongress:

    International Congress & Exposition ; 1995



    Erscheinungsdatum :

    1995-02-01




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Print


    Sprache :

    Englisch




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    Sferrazza, P. / Halter, R. / Stark, J. et al. | British Library Conference Proceedings | 1995


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    Operation of the HIP7011 J1850 Interface Device

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