The introduction of drive-by-wire systems into modern vehicles has generated new challenges for the designers of embedded systems. These systems, based primarily on microcontrollers, need to achieve very high levels of reliability and availability, but also have to satisfy the strict cost and packaging constraints of the automotive industry. Advances in VLSI technology have allowed the development of single-chip systems, but have also increased the rate of intermittent and transient faults that come as a result of the continuous shrinkage of the CMOS process feature size. This paper presents a low-cost, fault-tolerant system-on-chip architecture suitable for drive-by-wire and other safety-related applications, based on a triple-modular-redundancy configuration at the processor execution pipeline level.


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    Titel :

    A Fault-Tolerant Processor Core Architecture for Safety-Critical Automotive Applications


    Weitere Titelangaben:

    Sae Technical Papers


    Beteiligte:

    Kongress:

    SAE 2005 World Congress & Exhibition ; 2005



    Erscheinungsdatum :

    2005-04-11




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Print


    Sprache :

    Englisch




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