To meet new design objectives for drastic reductions in mass, size, and power consumption, the Flight Computer Development Group at JPL is participating in a design study and development of a light-weight, small-sized, low-power 3-D Space Flight Computer. In this paper, we will present a detailed design and tradeoff study of the proposed computer. We will also discuss a complete design of the multichip modules and their size, weight, and power consumption. Prelimimary thermal models will also be discussed.


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    Titel :

    (abstract) The Nest Generation of Space Flight Computers


    Beteiligte:
    Alkalaj, Leon (Autor:in) / Panwar, Ramesh (Autor:in)

    Erscheinungsdatum :

    1993-12-07


    Medientyp :

    Preprint


    Format :

    Keine Angabe


    Sprache :

    Englisch





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