This paper reports a Class S CCSDS recommendation Reed Solomon encoder circuit baselined for several NASA programs. The chip is fabricated using United Technologies Microelectronics Center's UTE-R radiation-hardened gate array family, contains 64,000 p-n transistor pairs, and operates at a sustained output data rate of 200 MBits/s. The chip features a pin selectable message interleave depth of from 1 to 8 and supports output block lengths of 33 to 255 bytes. The UTE-R process is reported to produce parts that are radiation hardened to 16 Rads (Si) total dose and 1.0(exp -10) errors/bit-day.


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    Titel :

    Space Qualified High Speed Reed Solomon Encoder


    Beteiligte:
    Gambles, Jody W. (Autor:in) / Winkert, Tom (Autor:in)


    Erscheinungsdatum :

    1993-01-01


    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Keine Angabe


    Sprache :

    Englisch




    Space Qualified High Speed Reed Solomon Encoder

    Gambles, J. / Winkert, T. / United States; National Aeronautics and Space Administration; Space Engineering Research Center | British Library Conference Proceedings | 1993


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    Troung, T. K. / Reed, I. S. / Deutsch, L. J. et al. | NTRS | 1985


    VLSI Reed-Solomon Encoder

    Liu, K. Y. | NTRS | 1983


    Control Circuit For Reed-Solomon Encoder

    Ross, Douglas | NTRS | 1992


    Single-Chip VLSI Reed-Solomon Encoder

    Truong, T. K. / Deutsch, L. J. / Reed, I. S. | NTRS | 1986