Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.


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    Titel :

    Rounding Technique for High-Speed Digital Signal Processing


    Beteiligte:

    Erschienen in:

    Erscheinungsdatum :

    01.08.1983



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch


    Schlagwörter :



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