At the on-set of this SBIR program, SYSTRAN had the vision of utilizing the IEEE (Institute of Electrical and Electronics Engineers) standard for SCI (Scalable Coherent Interface) as the basis for implementing a parallel computer configured from mostly COTS (Commercial Off The Shelf) components as a future distributed platform for avionics computations. In the course of this program, we formulated a design for a 6U-VME, PowerPC CPU-based, single board computer that would include SCI network interfaces as the networking mechanism. In addition, we designed specialized cache-memory controller that would implement the SCI protocol, thus allowing true distributed, shared-memory, multicomputing to be performed. We utilized the Chorus micro-kernel operating systems as the operating system for this design. Unfortunately, the market for SCI in avionics systems has been surpassed by ANSI Standard Fibre Channel high- bandwidth networking solutions. Fibre Channel is now being used on the AWACS and other aircraft and represents the market originally considered by SYSTRAN for this program. In 1997, we decided not to bring the technology designed in this program to the Phase III market.


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    Titel :

    COTS-Based Real-Time Avionics Parallel Computer (COTS Avionics)


    Beteiligte:
    G. J. Valentino (Autor:in) / K. S. Lee (Autor:in)

    Erscheinungsdatum :

    1998


    Format / Umfang :

    87 pages


    Medientyp :

    Report


    Format :

    Keine Angabe


    Sprache :

    Englisch






    Impact of COTS on Military Avionics Architectures

    Carbonell, J. / Ostgaard, J. / Advisory Group for Aerospace Research and Development; Mission Systems Panel | British Library Conference Proceedings | 1997