The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.
Programmable high-performance IIR filter chip
01.06.1995
7 pages
Aufsatz (Zeitschrift)
Englisch
systolic arrays , clock speed , multiplier/accumulators , multiplying circuits , two's complement data , overflow detection , redundant number system , IIR filter chip , pipelining , programmable filters , gate array , infinite impulse response , IIR filters , logic arrays , redundant number systems , GEC Plessey Semiconductors CLA78000 series , design for testability , 16 bit , digital filters , 30 MHz , systolic array architecture
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