The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    A Re-Programmable Motion Control Chip

    Habinc, S. / Ekergarn, J. / Glembo, K. et al. | British Library Conference Proceedings | 2011


    Filter Bank Analyser Using Programmable IIR Filters

    Nini, G. / Zimpfer-Jost, V. / Buck, K. | British Library Conference Proceedings | 2004


    System of a programmable-chip-based image-processing system

    Wu, F. / Smith, J.S. / Tickle, A.J. et al. | British Library Online Contents | 2013


    Design and Implementation of a Programmable Stack Filter

    Lakamsani, P. V. / Yang, R. / Zeng, B. et al. | British Library Conference Proceedings | 1994