This paper proposes an error compensation circuit for fixed-width multiplier based on probability and computer simulation (PACS), whereas the solution provides highest accuracy, low power consumption with high speed. Being highly accurate, the proposed PACS approach is area-effective as compared to Multilevel conditional Probability (MLCP) method. The proposed 8×8 bit fixed width multiplier is designed using Xilinx. Significant reduction in FPGA resources, delay and power can be achieved using fixed width multiplier with PACS instead of MLCP method.


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    Titel :

    Probablity and simulation based design of fixed width multiplier


    Beteiligte:
    Keote, R. S. (Autor:in) / Meshram, P. S. (Autor:in) / Karule, P. T. (Autor:in)


    Erscheinungsdatum :

    01.04.2017


    Format / Umfang :

    464554 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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