We describe a fast, abstract method for reverse engineering (RE) field programmable gate array (FPGA) look-up-tables (LUTs). Our method has direct applications to hardware (HW) metering and FPGA fingerprinting, and our approach allows easy portability and application to most L UT based FPGAs. Unlike conventional RE methodologies that rely on vendor specific code (like Xilinx XDL), tools, configuration files, components, etc., our methodology is not dependent on any specific FPGA or FPGA computer aided design (CAD) tool. We use generic hardware description language (HDL) code based on specially connected CASE statements to program the L UTs on a target FPGA. Our specially connected CASE statements allow us to guide placement of L UT functions on successive synthesis runs. This enables us to quickly determine which bits in the FPGA 's configuration file match to FPGA L UT bits. After we know which bits are L UT bits, we can go further and match specific LUT bits to specific bits in the configuration file, thereby creating a one-to-one mapping between every L UT memory cell and its matching bit in the configuration file. In this paper we present our CASE statement functions for performing one-to-one mapping of all FPGA L UT memory cell bits to specific configuration file bits. We have successfully applied our methods to several 7000 series Xilinx and Intel (Altera) FPGAs.
Fast FPGA Reverse Engineering for Hardware Metering and Fingerprinting
28.08.2023
1126312 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
FAST STAR TRACKER HARDWARE IMPLEMENTATION ON A FPGA DEVICE
TIBKAT | 2020
|Hardware Layout of Independent Metering Control
Springer Verlag | 2024
|FPGA macht mobil. Flexible Hardware-Plattform
Tema Archiv | 2002
Additively manufactured thermoplastic metering pin with slots for retention hardware
Europäisches Patentamt | 2021
|