A three gigasample per second (GSPS) digital wideband receiver that operates in a 1.25-GHz instantaneous bandwidth (IBW) is proposed. In addition to building such systems, offloading of computation-intensive tasks to a combination of specialized hardware accelerators such as graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) to increase the overall receiver's dynamic performance is analyzed. The receiver detects up to 15 signals with a maximum attainable instantaneous dynamic range (IDR) of 62.5 dB before the next set of data arrives for processing.


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    Titel :

    Multiple Signal Detection Digital Wideband Receiver using Hardware Accelerators


    Beteiligte:
    George, K. (Autor:in) / Chen, C-I H. (Autor:in)


    Erscheinungsdatum :

    2013-04-01


    Format / Umfang :

    3804410 byte




    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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