DDR3L based memory bus design conventionally employs termination on the command, address and control bus. This paper discusses the effort to optimize the bus to function within the specifications without these terminations. Signaling and power sensitivities are discussed at various bus speeds.
Trade-offs in CAC memory terminations
2016-09-01
1403562 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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