Radiation-hardened optically reconfigurable gate arrays have been developed for use in space embedded systems. An optically reconfigurable gate array consists of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI, which is one type of radiation-hardened SRAM-based field programmable gate array (FPGA). However, optically reconfigurable gate arrays have the important feature of faster scrubbing operations than that of radiation-hardened SRAM-based FPGAs. Therefore, the soft-error-tol er anees of the configuration memories of optically reconfigurable gate arrays become much higher than those of FPGAs. However, the calculation load of a lot of holographic memory patterns on a personal computer is extremely heavy. This paper therefore presents a hardware accelerator using an FPGA. The Vivado-high-level synthesis tool (Xilinx Inc.) has been used for development. Its operation speed was improved drastically from 1,590 ms to 3.12 ms while its power consumption for calculations has been decreased drastically from 55 W to 4.4 W.


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    Titel :

    FPGA hardware accelerator for holographic memory calculations for optically reconfigure gate arrays


    Beteiligte:
    Ito, Yoshizumi (Autor:in) / Watanabe, Minora (Autor:in)


    Erscheinungsdatum :

    01.11.2017


    Format / Umfang :

    931523 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    FPGA Based Hardware Accelerator for Parallel Robot Kinematic Calculations

    Karpiel, Grzegorz / Gac, Konrad / Petko, Maciej | BASE | 2015

    Freier Zugriff


    Robot Would Reconfigure Modular Equipment

    Purves, Lloyd R. | NTRS | 1993



    FPGA-based hardware accelerator for high-performance data-stream processing

    Lysakov, K. F. / Shadrin, M. Y. | British Library Online Contents | 2013