Concepts for the packaging of a massively parallel signal processor for a radar surveillance satellite are investigated. The signal processor assumed employs 32 custom processor dice arranged as a parallel computer. The significant packaging challenge is interconnection of the various processor dice while maintaining a stringent time-of-flight requirement for the high speed signals. The total number of interconnects for the 32 dice is approximately 12,800 where the high speed interconnect requirement concerns approximately 4800 interconnects. Various packaging and routing strategies are investigated with a statistical comparison of the routes provided.


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    Titel :

    Packaging of a massively parallel signal processor for spaceflight


    Beteiligte:
    Johnson, D.C. (Autor:in) / Forman, S.E. (Autor:in) / Retherford, L.L. (Autor:in) / Mendenhall, L.M. (Autor:in) / Hein, T.L. (Autor:in)


    Erscheinungsdatum :

    2000-01-01


    Format / Umfang :

    619495 byte





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Packaging of a Massively Parallel Signal Processor for Spaceflight

    Johnson, D. C. / Forman, S. E. / Retherford, L. L. et al. | British Library Conference Proceedings | 2000


    The Massively Parallel Processor

    D.H. Schaefer / J.R. Fischer / K.R. Wallgren NASA Goddard Space Flight Center et al. | AIAA | 1982


    The massively parallel processor

    SCHAEFER, D. / FISCHER, J. / WALLGREN, K. | AIAA | 1980


    Connected component labelling on the BLITZEN massively parallel processor

    Ziavras, S. G. | British Library Online Contents | 1993