A /spl Sigma//spl Delta/ modulator designed specifically for extended temperature applications is reported. The design is fabricated in a 3.3-V 0.5 /spl mu/m SOS-CMOS process and incorporates a 2-2 cascade architecture allowing operation as either a 2/sup nd/- or 4/sup th/-order modulator. Experimental data for both modulator configurations are presented including dynamic range (or effective resolution), signal-to-noise ratio and total harmonic distortion over a temperature range of 25/spl deg/C to 225/spl deg/C. The design obtains an effective resolution of /spl sim/16 bits at 25/spl deg/C and /spl sim/12 bits at 225/spl deg/C, both at a digital output rate of 2 KS/s. Specific design details associated with high temperature operation are discussed including architectural issues, device sizing, and modulator noise. In addition, a digital decimation filter designed for use with the modulator and implemented in both software and in a field programmable gate array is summarized. This paper reports the first 4/sup th/-order /spl Sigma//spl Delta/ modulator fabricated in an SOI/SOS process and demonstrates the feasibility of high resolution data conversion at elevated temperatures.


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    Titel :

    A high resolution, extended temperature sigma delta ADC in 3.3 V 0.5 /spl mu/m SOS-CMOS


    Beteiligte:
    Ericson, M.N. (Autor:in) / Bobrek, M. (Autor:in) / Bobrek, A. (Autor:in) / Britton, C.L. (Autor:in) / Rochelle, J.M. (Autor:in) / Blalock, B.J. (Autor:in) / Schultz, R.L. (Autor:in)


    Erscheinungsdatum :

    2004-01-01


    Format / Umfang :

    827622 byte





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




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