A major problem in phase-locked loop (PLL) design is to meet the requirements of both fast signal acquisition and good synchronous mode performance. This relation is reviewed for different types of phase comparators. As a result a new phase-and-frequency comparator is proposed. This comparator is based on an up-down counter principle and can be considered as an adaptive acquisition control circuit. The analysis of a PLL with the proposed phase comparator is based on an exact calculation method for the pull-in time. It is shown that fast signal acquisition is possible without affecting the filtering properties of the loop. Experimental results are given of the acquisition behavior of a second-order type-2 loop which show a good correspondence with the theoretical analysis.


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    Titel :

    Improved Phase-Locked Loop Performance with Adaptive Phase Comparators


    Beteiligte:

    Erschienen in:

    Erscheinungsdatum :

    01.05.1982


    Format / Umfang :

    3054256 byte




    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




    All digital phase-locked loop

    Jurgo, Marijan | BASE | 2013

    Freier Zugriff

    Gated Phase-Locked Loop Study

    Eisenberg, Barry R. | IEEE | 1971


    Phase Locked Servo Loop Circuit

    S. A. Miller | NTIS | 1973


    Differential vector phase locked loop

    Brewer, James / Raquet, John | IEEE | 2016