It is necessary to insert a switching delay time in pulse width modulation(PWM) voltage-fed inverters to avoid the short through of phase bridge. This causes well known dead time effect which distorts the output voltage and current. This paper puts forward a new three-level dead-time compensation method, which compensates dead time, turn on and off delay and forward voltage drop. A three-level inverter hardware platform was built based on FPGA and DSP, and the relevant experiment has been done on the 30kW three-phase induction motor. Experimental results verified the feasibility and correctness of the algorithm.


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    Titel :

    A novel dead-time compensation strategy of three-level inverter


    Beteiligte:
    Guo Jing (Autor:in) / Gong Xuegeng (Autor:in) / Zhao, Feng (Autor:in) / Wen, Xuhui (Autor:in)


    Erscheinungsdatum :

    01.08.2014


    Format / Umfang :

    1347643 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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