An interlocking data safe conversion method for formal verification and a translator. Two translators with same functions are developed by adopting different programming methods and programming languages. An input file of each of the translators at least comprises an interlocking information table in interlocking data, a device interface information table, a station yard description data and interlocking Boolean logic data. Consistency of output files of the two translators is compared to realize detection process failure.


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    Titel :

    INTERLOCKING DATA SAFE CONVERSION METHOD FOR FORMAL VERIFICATION AND TRANSLATOR


    Beteiligte:
    WEI MIN (Autor:in) / WANG YANQIN (Autor:in) / ZHANG MINGYAO (Autor:in) / WANG SHAOXIN (Autor:in) / YANG FAN (Autor:in) / LUI XIAO (Autor:in) / ZHANG CHENG (Autor:in) / ZHANG WENYAN (Autor:in)

    Erscheinungsdatum :

    04.07.2024


    Medientyp :

    Patent


    Format :

    Elektronische Ressource


    Sprache :

    Englisch


    Klassifikation :

    IPC:    B61L Leiten des Eisenbahnverkehrs , GUIDING RAILWAY TRAFFIC / G06F ELECTRIC DIGITAL DATA PROCESSING , Elektrische digitale Datenverarbeitung



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