In an embodiment, a method comprises: running, with a first core of a first multiprocessor system on chip (MPSoC) of a distributed computing architecture, a first process/thread on input data, the first process/thread pinned to the first core; storing, using a cache coherency fabric, first data in shared memory, the first data generated by the first process/thread; fetching, with a second process/thread pinned to a second core of a second MPSoC of the distributed computing architecture, the first data from the shared memory; and running, with the second core of the second MPSoC, the second process/thread on the first data.
DISTRIBUTED COMPUTING ARCHITECTURE WITH SHARED MEMORY FOR AUTONOMOUS ROBOTIC SYSTEMS
2023-10-26
Patent
Elektronische Ressource
Englisch
IPC: | B60W CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION , Gemeinsame Steuerung oder Regelung von Fahrzeug-Unteraggregaten verschiedenen Typs oder verschiedener Funktion |
DISTRIBUTED COMPUTING ARCHITECTURE WITH SHARED MEMORY FOR AUTONOMOUS ROBOTIC SYSTEMS
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