Examples of techniques for fault diagnosis for fault tolerant chassis architecture systems are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes receiving, by a processing device, a control variable for the system. The method further includes receiving, by the processing device, a measured variable for the system. The method further includes calculating, by the processing device, a residual based at least in part on the control variable and the measured variable. The method further includes performing, by the processing device, a fault diagnosis to detect a fault in the system based at least in part on the residual.


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    Titel :

    FAULT DIAGNOSIS FOR FAULT TOLERANT CHASSIS ARCHITECTURE SYSTEMS


    Beteiligte:
    YAO YIXIN (Autor:in) / SMITH LANCE A (Autor:in) / YU LEIBING (Autor:in)

    Erscheinungsdatum :

    2019-06-20


    Medientyp :

    Patent


    Format :

    Elektronische Ressource


    Sprache :

    Englisch


    Klassifikation :

    IPC:    B60T Bremsanlagen für Fahrzeuge oder Teile davon , VEHICLE BRAKE CONTROL SYSTEMS OR PARTS THEREOF / G01R Messen elektrischer Größen , MEASURING ELECTRIC VARIABLES / G07C TIME OR ATTENDANCE REGISTERS , Zeit- oder Anwesenheitskontrollgeräte



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