Aspects of the present disclosure include a symmetric direct current (DC) link capacitor having a low parasitic equivalent series L inductance (ESL). An exemplary capacitor may include one or more positive-dielectric-negative (PDN) stacks having a positive electrode layer, a negative electrode layer, and a dielectric layer between the positive electrode layer and the negative electrode layer. The first contact layer is electrically coupled to the positive electrode layer on the side wall of the one or more PDN stacks, and the second contact layer is electrically coupled to the negative electrode layer on the side wall of the one or more PDN stacks. The positive terminal is electrically coupled to the first contact layer, and the negative terminal is electrically coupled to the second contact layer.
本公开的方面包括具有低寄生等效串联L电感(ESL)的对称直流(DC)链路电容器。示例性电容器可以包括一个或多个正‑介电‑负(PDN)堆叠,堆叠具有正极层、负极层以及正极层和负极层之间的介电层。第一接触层电联接到一个或多个PDN堆叠侧壁上的正极层,第二接触层电联接到一个或多个PDN堆叠侧壁上的负极层。正极端子电联接到第一接触层,负极端子电联接到第二接触层。
Low parasitic equivalent series L-inductor symmetric DC link capacitor
低寄生等效串联L-电感对称直流链路电容器
29.10.2024
Patent
Elektronische Ressource
Chinesisch
LOW PARASITIC EQUIVALENT SERIES L-INDUCTANCE (ESL) SYMMETRIC DIRECT CURRENT (DC) LINK CAPACITOR
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