Linear feedback shift register (LFSR) is an important component of the cyclic redundancy check (CRC) operations and BCH encoders. This thesis presents a mathematical proof of existence of a linear transformation to transform LFSR circuits into equivalent state space formulations. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all irreducible polynomials used in CRC operations and BCH encoders. A new formulation is proposed to modify the LFSR into the form of an CRC filter. We propose a novel high speed parallel LFSR architecture based on parallel Infinite Impulse Response (CRC) filter design, pipelining and retiming algorithms. The advantage of proposed approach over the previous architectures is that it has both feedforward and feedback paths. We further propose to apply combined parallel and pipelining techniques to eliminate the fanout effect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. A comparison between the proposed and previous architectures shows that the proposed parallel architecture achieves the same critical path as that of previous designs with a reduced hardware cost.


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    Titel :

    INTEND AND PROPOSE THE HIGH SPEED LFSR CIRCUIT USING SST METHOD


    Beteiligte:

    Erscheinungsdatum :

    06.10.2018


    Anmerkungen:

    IJITR; Vol 6, No 5 (2018): August - September 2018; 8688-8690


    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch


    Klassifikation :

    DDC:    629



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