Radio resource management (RRM) is critical in 5G mobile communications due to its ubiquity on every radio device and its low latency constraints. The rapidly evolving RRM algorithms with low latency requirements combined with the dense and massive 5G base station deployment ask for an on-the-edge RRM acceleration system with a tradeoff between flexibility, efficiency, and cost-making application-specific instruction-set processors (ASIPs) an optimal choice. In this work, we start from a baseline, simple RISC-V core and introduce instruction extensions coupled with software optimizations for maximizing the throughput of a selected set of recently proposed RRM algorithms based on models using multilayer perceptrons (MLPs) and recurrent neural networks (RNNs). Furthermore, we scale from a single-ASIP to a multi-ASIP acceleration system to further improve RRM throughput. For the single-ASIP system, we demonstrate an energy efficiency of 218 GMAC/s/W and a throughput of 566 MMAC/s corresponding to an improvement of 10x and 10.6x, respectively, over the single-core system with a baseline RV32IMC core. For the multi-ASIP system, we analyze the parallel speedup dependency on the input and output feature map (FM) size for fully connected and LSTM layers, achieving up to 10.2x speedup with 16 cores over a single extended RI5CY core for single LSTM layers and a speedup of 13.8x for a single fully connected layer. On the full RRM benchmark suite, we achieve an average overall speedup of 16.4x, 25.2x, 31.9x, and 38.8x on two, four, eight, and 16 cores, respectively, compared to our single-core RV32IMC baseline implementation.
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures
2021-01-01
Aufsatz (Zeitschrift)
Elektronische Ressource
Englisch
5G mobile communication , Application-specific instruction-set processor (ASIP) , Benchmark testing , long short-term memory (LSTM) , machine learning , Multicore processing , neural network , Program processor , radio resource management (RRM) , recurrent neural network (RNN) , Resource management , RISC-V , Task analysi , Throughput
DDC: | 629 |
RISC architectures as a multiprocessor base
AIAA | 1987
|A RISC-Style Hardware Accelerator for Operating Systems
British Library Online Contents | 1999
|Automatic Functionality Assignment to AUTOSAR Multicore Distributed Architectures
SAE Technical Papers | 2016
|Validation of Securely Partitioned Systems over Multicore Architectures Based on XtratuM
British Library Conference Proceedings | 2013
|