In this paper, a Field-Programmable Gate Array (FPGA) based digital speed control scheme is presented, that is developed to overcome the drawbacks existing in the previous speed control schemes, which were proposed for switched reluctance motor (SRM) drives. It is based on discrete P, PI and PID control algorithm, and requires simple mathematical models. The scheme is implemented by using a XC2S300E FPGA. The real-time experimental results given in this paper show that the speed control method proposed could provide accurate speed control and over a wide range of speeds, and can also perform accurately at different operating conditions (steady state/transient operation under soft chopping mode). The closed loop SRM speed control system is seen to achieve 6.2 RPM speed accuracy, depending on the needed operating speed range, with a step response settling time of 0.25 to 1.05 seconds. Complete descriptions of the experimental system along with FPGA implementation are presented.


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    Titel :

    Digital speed controller implementation for a switched reluctance motor drive using FPGA


    Beteiligte:

    Erscheinungsdatum :

    01.01.2006


    Anmerkungen:

    International Journal for Engineering Modelling ; ISSN 1330-1365 (Print) ; ISSN 1849-8671 (Online) ; Volume 19 ; Issue 1-4


    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Klassifikation :

    DDC:    629



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