GMV is in charge of developing the GNC subsystem of HERA mission, currently going through Phase C. At the end of Phase A of the mission, it was identified the lack of any dedicated avionics platform for the implementation of hardware accelerated image processing algorithms required by the spacecraft autonomous navigation strategy. The hardware solution proposed by GMV in order to whitstand the demanding mission GNC requirements is in the form of a dual purpose avionics processing board for image processing and interface control (including management of interfaces with OBC and in-flight reprogramming): HERA Image Processing Unit (HERA IPU). The main drivers of HERA IPU design were the nominal and redundant SpaceWire I/F with the HERA S/C OBCs, and the ability to accommodate and accelerate in hardware the required image processing algorithms having as input images taken by a navigation camera. The HERA Image Processing Unit provides isolation of Image Processing Function and Interfaces Function, as it is relying on a two FPGAs architecture, with allocated external volatile and non-volatile memories. It is composed of one small and reliable European FPGA with rad-hard equivalent, BRAVE NG-Medium, dedicated to interfaces control and monitoring and the other one is a powerful FPGA to perform as computer vision co-processor. The current Processing FPGA is the Virtex-5 VFX130T, with its space equivalent component the high-density rad-hard V5QV FPGA. The SpaceWire interfaces allow TM/TC exchange between HERA IPU and two devices/instruments using nominal and redundant SpaceWire links (nominally 2 on-board computers, but the scenario can be adapted to only one on-board computer and one navigation camera). The design and development of the computer-vision algorithms for HERA IPU are facilitated by the architectural design of the processing FPGA code, which provides an internal interfacing wrapper to integrate the required image processing module satisfying a client-consumer simple interface. HERA IPU also includes pre-processing functions for the image received from navigation camera. The two FPGAs included by HERA IPU allow flexibility and many options for the design and implementation of complex functionalities, such as high-data rate interfaces management and hardware accelerators. Different computer-vision accelerators which are not used in the same moment of time can be used during the mission by replacing bitstreams in the processing FPGA in-flight to save a potentially needed second FPGA unit. The image processing algorithms envisaged by HERA GNC strategy depend on the phase of the mission, and include as minimum: LAMB (maximum correlation with a lambertian sphere – providing the position of the asteroid in the Field of View of the camera) and RelNav Feature Tracking (significant features are extracted from the navigation image, and afterwards compared with the features extracted from previous image in order to find their correspondence). The unit was validated as TRL 4/5 Elegant breadboard, while the validation of a fully scaled Engineering Model is expected to be finished mid 2021. The roadmap towards flight hardware is deemed with high probability of success, as all the electronic components selected for the engineering model have space qualified correspondents.


    Zugriff

    Download


    Exportieren, teilen und zitieren



    Titel :

    Reconfigurable Co-Processor for Spacecraft Autonomous Navigation


    Beteiligte:
    P. Bajanaru (Autor:in) / R. Domingo Torrijos (Autor:in) / D. Gonzalez-Arjona (Autor:in) / F.A. Stancu (Autor:in) / C. Onofrei (Autor:in) / M. Marugan Borelli (Autor:in) / R. Chamoso Rojo (Autor:in) / C.G. Mihalache (Autor:in)

    Erscheinungsdatum :

    2021-06-14



    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Klassifikation :

    DDC:    629





    Autonomous landmark based spacecraft navigation system

    Miller, J. K. / Cheng, Y. | NTRS | 2003




    Autonomous Orbit Navigation of Interplanetary Spacecraft

    Yim, J. / Crassidis, J. / Junkins, J. et al. | British Library Conference Proceedings | 2000