One of the biggest challenges in sensor technology at the moment relates to achieving cost-effectiveness and being able to integrate several functions on a single piece of silicon without sacrificing reliability and performance. Once the sensors' production volumes reach larger scales, cost-effectiveness can be improved in many ways. Reducing the size of the sensor has a direct correlation to a lowering of unit costs. Increasing the wafer size increases the number of sensors that can be built on the wafer, while the cost of processing the wafer stays essentially the same as with smaller 'wafers provided that the production line's capacity is used to a satisfactory degree. The performance and reliability of sensors made using traditional wet etching techniques may be good but reducing the sensor's size is hardly straightforward. In order to be cost-effective, wet etching often requires the use of extremely thin wafers, which makes increasing the wafer size problematic. The limitations of traditional sensor manufacturing technologies can be overcome by using high aspect ratio (HAR) structures, and HAR structures currently represent the best way to reduce the die size. Unlike in anisotropic wet etching, the entire surface area of the piece of silicon can be made use of, as the structures are separated by narrow RIE-etched trenches. If an SOI wafer This technique can also be used to create anti-stick structures for the moving parts of the sensor, in which case a narrow air gap can be used underneath the membranes, for example. In addition, HAR structures can be used to produce extremely thin sensors which would not be possible with wet etching techniques. Once the wafer that contains the sensor element is sealed using another silicon wafer, the structure can be easily thinned using rubbing techniques borrowed from semiconductor technology. HAR technology also enables full advantage to be taken of the possibilities presented by SOI: in the manufacture of SOI wafers, it is possible to introduce tailored buried structures in the wafer. This opens up new vistas in terms of manufacturing high-performance sensors that integrate multiple functions. This presentation focuses on SOI technology that enables HAR structures with DRIE processing.
Silicon technology enabling cost effective HAR structures
Einsatz der Siliziumtechnologie zur Erzielung kostengünstige HAR-Strukturen
2007
9 Seiten, 5 Bilder, 3 Quellen
Conference paper
English
Silicon Technology enabling Cost effective HAR Structures
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