The authors describe the NIP-III image processor, which can execute a wide variety of general image processing operations for automobile industry manufacturing applications. Sixteen processing units having the same architecture are connected in rows. Individual users can input desired instructions to each unit and also freely change the bus lines linking the units. The processing units are implemented by gate-array large-scale integrated circuits and can perform the arithmetic and logic functions needed for image processing. A high processing speed has been achieved without increasing the size of the circuits. The authors present the hardware architecture of the NIP-III and describe its processing capabilities.


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    Titel :

    Development of a high-speed image processor


    Weitere Titelangaben:

    Entwicklung eines Hochgeschwindigkeits-Bildprozessors


    Beteiligte:
    Nohsoh, K. (Autor:in) / Akutagawa, K. (Autor:in)


    Erscheinungsdatum :

    1988


    Format / Umfang :

    6 Seiten, 5 Quellen


    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Print


    Sprache :

    Englisch




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