This paper presents the Fault Tolerant Computer System that has been developed and tested by Matra Marconi Space in the framework of European space shuttle HERMES project. This system has been designed to cope with high safety and reliability requirements (FO/FS and less than 10-6 for the probability of a catastrophic event induced by a system failure). The system is composed of 4 tightly synchronised computers running in parallel, with each computer broadcasting its input and output data towards the other computers implementing a fault masking concept based on a bit-to-bit vote. The paper presents the major requirements and the rationale that led to the actual architecture. It provides a detailed technical description of the system, addressing functional, hardware and software aspects. It provides information about the development activities and presents the results and lessons learned.
Development of a fault tolerant computer system for the HERMES space shuttle
Entwicklungs eines fehlertoleranten Rechnersystems für das Hermes-Raumfahrzeug
1993
6 Seiten, 6 Bilder
Aufsatz (Konferenz)
Englisch
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|Hermes-450 Fault-Tolerant Design Concept
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|Fault-tolerant computer system
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|A Fault-Tolerant Computer for Space Applications
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|