A computer architecture has been developed to implement lane sensing in real-time on a vehicle. This system has been evaluated in the laboratory and successfully operated on a vehicle. The system has a 0.200 second processing time with 0.233 second delay, which translates into five images processed per second. Inspection of the timing diagram provides information about the bottlenecks in the system. Updating the look-up table for intensity normalization takes one full frame period or two fields. This time could be reduced by generating a histogram only for the first field of the image during the first frame period, then updating the look-up table during the second field of that frame period. This will eliminate one full period from the total processing time. The M68030 microprocessor spends three frame periods for processing the image . Most of the time is spent in searching the frame-stores for lane boundary information. This part of the algorithm can be made faster by developing custom electronics tailored for such searching. As a result, the authors can either run the same algorithm faster, or execute a more complex algorithm in the same time.
Computer architecture and implementation of vision-based real-time lane sensing
Die Rechnerarchitektur und Implementierung einer Echtzeit-Straßenbeobachtung mittels Computer Vision
Intelligent Vehicles Symposium, 1992 ; 202-206
1992
5 Seiten, 3 Bilder, 1 Tabelle, 5 Quellen
Aufsatz (Konferenz)
Englisch
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