The devices which will be described here are a new generation of multiplexers designed as switched-FET direct readouts (DRO) charge-integration nodes of very low capacitance for low background flux detectors. Based on the success of the NICMOS program, they have been designed and produced using processes optimized for operation of the devices at temperatures below 10 K with significantly lower noise than devices produced by non-optimized processes. A set of special features is incorporated, including an all-PMOS unit cell configuration, but with CMOS decoding of address signals and other logic levels. A number of lot splits were made in the production process to determine the best device types for low-temperature noise performance. Several of the successful splits were tested for various device characteristics.
256x256 switched-FET multiplexer for spaceborne astronomical applications
Geschaltete 256x256-FET-Multiplexer für astronomische Weltraumanwendungen
1992
9 Seiten, 14 Bilder, 6 Quellen
Aufsatz (Konferenz)
Englisch
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