Evaluation and refinement of system models often require modifications in the model that follow concrete rules. In this work, a method for a flexible automation of such transformation steps will be presented. It allows savings in development time and reduces the error proneness. Therefore, a tool for rule based manipulation of VHDL design descriptions has been extended to enable its use with system models in C++ and SystemC. An automotive electronics application, the integration of SystemC modules into a MATLAB/Simulink simulation by automatic wrapper generation, will show its use in the design process. Section 1 explains the underlying design flow. In Section 2 the transformation framework is presented in detail. Section 3 deals with related work and shows the problems in the present case. In Section 4, the C++/SystemC front-end is described, and in Section 5, an automotive electronics example shows how the new possibilities can be used in the design process. Finally, in Section 6, the results are summed up and a short outlook on future work is given.
Automatic transformation of system models in automotive electronics
Automatische Übertragung von Systemmodellen in fahrzeugspezifische Elektronik
2009
12 Seiten, 7 Bilder, 1 Tabelle, 18 Quellen
Aufsatz (Konferenz)
Englisch
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