The San Fransisco Bay Area Rapid Transit District (BART) is a computer-operated train control system. This system is currently undergoing a major upgrade to improve performance and maintainability. The new BART system will comprise: a Central Computer System (CCS) and a Process Input/Output system (PTO). This paper will focus on the PIO design. The PIO communicates with the CCS over a redundant communication link. It is responsible for translating CCS commands related to train and facilities control into signals to the BART plant, and for observing and reporting plant status. Although not a component of the safety system, the PIO is critical to revenue service. Consequently, the PIO has been allocated a stringent availability requirement. This requirement is unachievable with non-redundant hardware. The PIO contains a dual redundant processor that communicates with a cross-strapped input/output subsystem. One processor is designated the Primary and the other is the Shadow. The Primary Processor performs the PIO function while the Shadow provides checking of the Primary and serves as a hot standby should the Primary fail. This architecture was chosen to provide the desired availability and to facilitate repair.
A highly available microprocessor-based plant controller
Ein sehr zuverlaessiges Steuersystem auf Basis eines Mikroprozessors
1983
5 Seiten, 3 Bilder
Aufsatz (Konferenz)
Englisch
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