The CCD Stereo Camera is a principal science payload on board the Chang'E-1 (CE-1) satellite, developed and launched by China for the first Lunar Exploration Program. The principal task of the camera is to take image of the lunar surface in the visible band and obtains three-dimensional lunar terrain. The CCD Stereo Camera is designed based on threelinear array photogrammetric theories. The focal plane of the camera is comprised of a frame transfer CCD with size of 1024x1024 pixels. There are only three lines to be used to form a three-linear array, and the other lines are not used. The timing and control circuits of the camera are designed based on FPGA. An Actel's anti-fuse based FPGA, A1020B, is available, but the speed and logical resources of the device both are limited. This paper describes the design requirements, considerations and trade-off subject to the constraints. Especially, A novel logic circuit is introduced to generate the pulses with width of about 10ns~20ns with constraint of 8MHz external clock, which is used to design correlated double sampling (CDS) control signals and CCD reset signal. Finally, the result of flying verifications on-board of the timing and control circuits are also described.


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    Titel :

    Development of control circuits for the CCD stereo camera of Chang'E-1 satellite based on FPGA


    Beteiligte:
    Duan, Yong-qiang (Autor:in) / Wen, De-sheng (Autor:in) / Gao, Wei (Autor:in) / Zheng, Pei-yun (Autor:in) / Zhao, Bao-chang (Autor:in)

    Kongress:

    International Symposium on Photoelectronic Detection and Imaging 2011: Space Exploration Technologies and Applications ; 2011 ; Beijing,China


    Erschienen in:

    Erscheinungsdatum :

    2011-08-15





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Development of control circuits for the CCD stereo camera of Chang'E-1 satellite based on FPGA [8196-62]

    Duan, Y. / Wen, D. / Gao, W. et al. | British Library Conference Proceedings | 2011


    Two approaches to improve FPGA performance for the stereo camera of the Chang'E-1 satellite

    Duan, Yongqiang / Wen, Desheng / Gao, Wei et al. | IEEE | 2013



    Chang'e-2 survole Toutatis

    Online Contents | 2013


    The thermal design and numerical results of chang'e 1 satellite

    Xinbin, Hou / Li, Wang / Li, Xu et al. | AIAA | 2006