In this paper, a 12-bit 50MHz Pipelined Low-Voltage ADC is presented, which consists of 8-stage-pipelined low resolution ADCs and a 4-bit flash ADC. Several critical technologies are used to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, gain-boosted telescopic OTA and so on. Finally the whole system is taped out in SMIC with its 0.13 um process successful, the test result testified all the specifications are well satisfied.
12-Bits 50 MHz Pipelined Low-Voltage ADC Design
2008 Congress on Image and Signal Processing ; 4 ; 475-479
2008-05-01
498636 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
Online Contents | 1998
Online Contents | 1998
Verifying a pipelined microprocessor
IEEE | 2000
|Verifying a Pipelined Microprocessor
British Library Conference Proceedings | 2000
|Programable Pipelined-Image Processor
NTRS | 1986
|