Hardware-in-the-loop (HIL) test provides a time saving and safe environment for testing high-power electronic systems. But the main difficulty for the HIL test of power electronic system lies on the modeling of the complex and high-power system. This paper proposes a modeling method of the electrical system of high-speed train. With this method, the HIL test platform using field-programmable gate array boards is built. Besides, in order to meet the computing power requirement of the system modeling, we simulate the whole system using two dSPACE simulators and inside each dSPACE simulator, a multiprocessor system is achieved through Gigalink connection. The whole HIL system can be used to evaluate both the hardware and software performance of traction control unit and auxiliary control unit. The HIL results under steady state and transient conditions demonstrate modeling accuracy and provide a detailed insight into its development.


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    Titel :

    A System-Level FPGA-Based Hardware-in-the-Loop Test of High-Speed Train


    Beteiligte:
    Liu, Chen (Autor:in) / Guo, Xizheng (Autor:in) / Ma, Rui (Autor:in) / Li, Zhongliang (Autor:in) / Gechter, Franck (Autor:in) / Gao, Fei (Autor:in)


    Erscheinungsdatum :

    2018-12-01


    Format / Umfang :

    2832995 byte




    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    FPGA based hardware in the loop test platform of small size UAV

    Shih, Ta-Ming / Chang, Ho-Chung | Tema Archiv | 2009


    Double-safety interlocking loop for high-speed train door system

    TANG JIANGZHOU / ZHU JINLONG / JU XIAO et al. | Europäisches Patentamt | 2022

    Freier Zugriff


    High Speed Train System

    PARSLEY JOSEPH | Europäisches Patentamt | 2018

    Freier Zugriff

    Ultra high speed test CRH (China Railway High-Speed) train bogie

    WANG XINGYU / LI GUODONG / ZHOU DIANMAI | Europäisches Patentamt | 2016

    Freier Zugriff