The application of field-programmable gate array (FPGA) in the hardware-in-the-loop simulation (HiLs) has enabled the time step reaching the range of hundreds of nanoseconds. However, the time performance of FPGA-based real-time simulation remains to be improved. In this article, a network analysis modeling method for FPGA-based real-time simulation of the power electronic converter is proposed. An ideal switching network unit, without requiring a large amount of memory, is used to determine the topology of the circuit and solve interface voltages/currents from the torn circuit. A parallel integration method is then implemented to obtain the status of the circuit element. At last, a diode-clamped three-level voltage source converter is used as a case study to demonstrate the effectiveness of the method. A 40-ns simulation step is finally achieved on the National Instruments (NI) FlexRIO PXIe-7975 platform. The accuracy of the proposed method is also verified against the results from MATLAB/Simulink.


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    Titel :

    A Network Analysis Modeling Method of the Power Electronic Converter for Hardware-in-the-Loop Application


    Beteiligte:
    Liu, Chen (Autor:in) / Bai, Hao (Autor:in) / Ma, Rui (Autor:in) / Zhang, Xinyue (Autor:in) / Gechter, Franck (Autor:in) / Gao, Fei (Autor:in)


    Erscheinungsdatum :

    2019-09-01


    Format / Umfang :

    2314575 byte




    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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