We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-μm CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.


    Zugriff

    Download


    Exportieren, teilen und zitieren



    Titel :

    CMOS full-adders for energy-efficient arithmetic applications


    Beteiligte:

    Erscheinungsdatum :

    2011-01-01


    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Klassifikation :

    DDC:    620 / 629




    Enhanced Architecture for Precision Adders

    G, Archana N / Kumari N, Prameela | IEEE | 2019



    Digital optical adders based on the photon echo effect [3239-54]

    Yashin, A. N. / SPIE | British Library Conference Proceedings | 1997


    Memory-Efficient Semi-Quasi-Arithmetic Coding

    Hong, D. / Eleftheriadis, A. | British Library Conference Proceedings | 2005


    Memory-efficient semi-quasi-arithmetic coding

    Hong, D. / Eleftheriadis, A. | IEEE | 2005